One of the goals in the fabrication of electrically erasable programmable read only memories (EEPROMs) is the production of memory circuits which are capable of storing a maximum amount of information using a minimum amount of semiconductor surface area. However, photolithographic limits imposed by conventional semiconductor processing technology impede the achievement of this goal. Thus, an inability to pattern and etch semiconductor features beyond current physical limits prevents a memory cell from being constructed having the desired minimum semiconductor surface area.
EEPROMs often use a floating gate avalanche injection MOS (FAMOS) structure to store program information. One solution to the problem of dimensioning a floating gate at minimum photolithographic limits is provided by the use of a single sidewall floating gate formed on a sidewall of the control gate. However, since such a floating gate is merely added to a sidewall of an ordinary photolithographically defined control gate, the resulting structure is generally no smaller than a conventional FAMOS structure and achieves no greater memory storage capabilities. Accordingly, a need exists for a memory cell in which a floating gate structure is used to increase the storage capacity of the memory cell while maintaining the size of the cell at an acceptably small magnitude.